This invention relates to the field of solid state electronic devices and more precisely to the field effect transistor art.
An important factor in many metal-semiconductor field effect transistor (MESFET) failure mechanisms has been determined to concern the location of and the magnitude of current crowding, near the top surface of the semiconductor material.
The geometry of a MESFET, coupled with standard active layer doping profiles, produce current crowding regions in at least two distinct areas near the surface of such device. This current crowding occurs on the leading edges of the source and drain elements or electrodes and if a recessed gate arrangement is used, current crowding also occurs on both sides of the gate. These current crowding areas are known to cause or contribute to surface related failure mechanisms including material migration, heat stresses, voltage breakdown, and other near surface deleterious phenomena.
The proximity of such currents to the transistor surface also makes careful surface preparation a necessity during transistor fabrication in order to limit the influence of current crowding-related failure mechanisms. This extra surface preparation activity leads of course, to lowered process yields and increased fabrication complexity. Some electronic devices, such as diodes, have in fact, shown that GaAs and other semiconductor materials will allow higher electric fields and power densities in their bulk regions than their best achievable surfaces will tolerate.
The patent art includes several examples of transistor structures which are of general background interest with respect to the present invention. Included in this art is the U.S. Pat. No. 4,769,338 of S. R. Ovshinsky et al which is concerned with a thin film field effect transistor and its fabrication. The transistor of the Ovshinsky et al invention differs from that of the present invention in its use of source and drain electrodes which are deposited over the semiconductor channel element in contrast with an underlying relationship for these elements in the present invention.
The patent art of interest also includes U.S. Pat. No. 4,782,032, issued to A. E. Geissberger et al, which is concerned with a fabrication arrangement for a self-aligned gallium arsenide transistor having a special Twin Gate interconnect arrangement. The Geissberger et al transistor is also not of the buried source and drain variety and in addition employs self aligned side contact members. Thereby the Geissberger transistor is distinguished from the transistor of the present invention.
The patent art of interest also includes U.S. Pat. No. 4,786,610 of L. Blossfeld which is concerned with a fabrication arrangement for an integrated circuit which employs a bipolar planar transistor having ion implanted N impurities. The absence of a field effect transistor in this integrated circuit distinguishes the present invention from the Blossfeld invention.
The patent art of interest also includes U.S. Pat. No. 4,843,024 which is issued to K. Ito and is concerned with a method for producing a Schottky gate field effect transistor including N+ regions formed by an ion implantation. The transistor of the Ito invention has a degree of similarity to the Geissberger et al transistor described above and does not employ the buried source and drain arrangement of the present invention.
The patent art of interest also includes U.S. Pat. No. 4,868,135 issued to S. Ogura et al and concerned with a method for fabricating a Bi-CMOS transistor device. The Ogura et al transistor employs an epitaxial or epi N layer and achieves a MOSFET type of transistor; however, the source and drain electrodes in this transistor are not of the buried type as in the present invention.
The patent art of interest also includes U.S. Pat. No. 4,962,054 issued to S. Shikata which is concerned with a method for fabricating a field effect transistor which employs spacers of differing thickness. The Shikata transistor employs a dissimilar drain to gate vs. source to gate spacing interval and is achieved with a self aligned fabrication arrangement that is similar to the Geissberger et al and Ito patents discussed above, but also does not employ a buried source and drain arrangement.
Also included in the patent art of general interest is U.S. Pat. No. 4,963,501 issued to F. J. Ryan et al. The Ryan patent is concerned with a method for fabricating semiconductor devices having submicron line widths. The Ryan et al transistor is also a self aligned device which uses substitutional gate processing, but is not of the buried source and drain arrangement included in the present invention.
The patent art of general interest also includes U.S. Pat. No. 4,956,308 issued to E. L. Griffin et al; this patent is concerned with the method for fabricating self aligned field effect transistors. As with the Geissberger et al and Ito transistors the Griffin et al transistor is not of the buried source and drain variety as in the present invention.
Also included in this patent art is U.S. Pat. No. 5,021,361 issued to J. Kinoshita et al which is concerned with the fabrication of a combination field effect transistor and opto-electronic device. The transistor of the Kinoshita et al invention is also of the top contact or overlaying source and drain type rather than the buried source and drain structure of the present invention.
These examples of prior transistor arrangements are therefore of the conventional metal-semiconductor field effect transistor (MESFET) type which employ overlaying source and drain locations or of the implanted MESFET type wherein implanted source and drain regions reside at the side of an epi layer.